One negative effect of transistor scaling for performance is that leakage power dramatically increases, becoming a significant design factor in advanced transistors. Transistor power dissipation at advanced nodes has shifted from mostly dynamic power dissipation to static leakage during standby modes of operation. Static leakage can now account for 40% or more of the total power consumption. Dynamic power includes switching power used for charging and discharging capacitors, and short circuit power related to nonzero rise and fall times of the input waveforms.
The subthreshold current has become the dominant leakage component for today's advanced node devices. This current is generated within the depletion region at the drain to well and source to well junctions of the device. These pn junctions are typically reverse biased allowing minority carrier drift/diffusion current, as well as electron-hole pair localized recombination. In addition, the high electric field can allow significant band-to-band tunneling current between the valence band and conduction band of the device. Subthreshold current becomes more significant as the device Vt is lowered.
As the channel length shrinks from generation to generation, Drain Induced Barrier Lowering (DIBL) also becomes a larger overall component of transistor leakage and performance degradation. In short channel devices, the electric field potential from the source and drain increases depletion in the channel, causing additional band bending which effectively lowers the device Vt, increasing subthreshold leakage current. The traditional transistor control technique to set Vt utilizes pocket (also known as “halo”) implants at the source/drain edge. Such halo implants introduce dopants into the transistor channel which in turn can result in excessive variations in Vt.